1. Field of the Invention
The present invention relates to a non-volatile memory circuit and to the corresponding manufacturing process and more particularly to a non-volatile memory device of the Flash type.
2. Description of the Related Art
Non-volatile memory electronic devices, for example of the Flash type, integrated on a semiconductor substrate typically have a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines.
Each single non-volatile memory cell in one form is a MOS transistor wherein the gate electrode, placed above the channel region, is floating, i.e., it has a high DC impedance towards all the other terminals of the same cell and of the circuit wherein the cell is inserted.
The cell also includes a second electrode, called a control gate, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly. This second electrode is driven by means of suitable control voltages. The other electrodes of the transistor are the usual drain and source terminals.
The cells belonging to a same word line share the electric line that drives the respective control gates, while the cells belonging to a same bit line share the drain terminals.
An architecture for non-volatile memory matrixes of the NOR type is for example shown in FIGS. 1-4.
In particular on a semiconductor substrate 1 a plurality of active areas 2 are formed wherein the memory cells will be formed. Groups G1 of active areas, wherein the active areas 2 are equidistant from each other, are separated by active areas 3 of greater dimension with respect to the active areas 2 and are spaced further from these groups of active areas.
Each active area 2, 3 is surrounded by an oxide layer called field oxide.
A photolithographic mask used to form these active areas 2, 3 is shown in FIG. 2.
After having formed at least one tunnel oxide layer and a first polysilicon layer on the semiconductor substrate 1, the floating gate electrodes of the memory cells 6 having width W are then defined, in this polysilicon layer, along a first direction.
After having formed at least one interpoly layer and a second polysilicon layer on the whole memory matrix, the second conductive layer, the second dielectric layer, the first conductive layer and the first dielectric layer are etched in sequence by means of a photolithographic mask until the semiconductor substrate 1 is exposed and the gate electrodes of the memory cells 6 having length L are completed.
In particular, with this latter etching step, in the second conductive layer word lines 4 of the matrix of memory cells 6 are defined. The portions of word lines aligned with the floating gate electrodes form control gate electrodes of the single memory cells 6.
A photolithographic mask used to form a plurality of word lines 4 is shown in FIG. 4.
In matrixes of memory cells with NOR architecture, groups 5 of memory cells 6 share a common source line 7. This common source line 7 is obtained by removing a portion of the oxide layer between adjacent active areas and by carrying out a dopant implantation in the semiconductor substrate 1.
To avoid too high of a resistance in the common source line 7, a contact region 8 must be inserted to contact the common source line 7. This contact region 8 is formed in correspondence with the active area 3, which has been provided with greater dimensions with respect to the active areas wherein the single memory cells are formed. In order to allocate the contact region 8 without electric interference problems, the common source line 7 will have to provide a widened pad 9 in correspondence with this contact regions 8.
Also the polysilicon layer forming the word lines 4 must thus provide a particular shaping to allow the insertion of the contact region 8 as shown in FIG. 1.
Ideally, the common source line 7 is generally self-aligned with the word lines and thus the word lines must be formed so as to follow the profile of the widened pad 9.
After having formed drain regions of the memory cells 6 inside the active areas 2, drain contacts 10 aligned with each other are formed, while the contact region 8 is formed in correspondence with the widened pad 9.
A photolithographic mask used to form the drain contacts and the contact region 8 is shown in FIG. 3.
In this type of NOR architecture, the selection of the single memory cell 6 occurs by placing the word lines of the cell 6 to be selected, and thus its control electrode, and one of the lines which are connected to the drain contact 10 of the cell 6 to be selected at a high potential, so that the current flow passes from the drain contact 10 to the contact region 8 through the common source line 7 as shown by the arrows A, B, and C of FIG. 1.
Although advantageous under several viewpoints, this first solution has several drawbacks.
In fact, when the dimensions of the memory cells 6 decrease, it is not possible to proportionally decrease the dimensions of the contact region 8, and thus of the relative widened pad 9, without causing malfunctions of the memory cells.
In consequence, not only the area dedicated to the contact region 8 is to be increased with respect to the dimension of a memory cell 6, but also the regularity with which the active areas 2, 3 of the memory cells are formed in correspondence with the contact region 8 is to be interrupted.
However, this interruption of the periodicity generates a structure that is highly sensitive to the aberrations of the projection optical system.
The technical problem underlying the present invention is that of providing a non-volatile memory electronic device having such structural characteristics as to enable forming the contact region of the common source line without increasing the dimensions of the memory matrix, maintaining the symmetry of the matrix of memory cells.